The configurable flip-flop defined in claim 1 wherein the configurable delay circuit comprises a programmable multiplexer having an output that is coupled to the first latch.ħ.
The configurable flip-flop defined in claim 4 wherein the second latch comprises: a data input coupled to the data output of the first latch a data output coupled to the flip-flop data output and a clock input coupled to the flip-flop clock input and operable to receive the clock signal from the flip-flop clock input.Ħ. The configurable flip-flop defined in claim 3 wherein the first latch comprises: a data input coupled to the flip-flop data input a data output and a clock input coupled to the configurable delay circuit and operable to receive the adjustable delayed version of the clock signal from the configurable delay circuit.ĥ. The configurable flip-flop defined in claim 1 further comprising a flip-flop data input coupled to the first latch, a flip-flop data output coupled to the second latch, and a flip-flop clock input operable to receive the clock signal.Ĥ. The configurable flip-flop defined in claim 1 further comprising a flip-flop clock input operable to receive the clock signal, wherein the configurable delay circuit is operable to receive the clock signal from the flip-flop clock input, and wherein the second latch is operable to receive the clock signal from the flip-flop clock input.ģ. A configurable flip-flop, comprising: first and second latches and a configurable delay circuit operable to receive a clock signal and operable to provide an adjustable delayed version of the clock signal to the first latch, wherein the second latch is operable to receive the clock signal.Ģ. High speed digital signal buffer and methodġ. Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the sameĭigital electronic circuit for translating high voltage levels to low voltage levelsĪpparatus and Method for Improving Storage Latch Susceptibility to Single Event UpsetsĪpparatus and Methods for Adjusting Performance of Programmable Logic Devices PROGRAMMABLE ARRAY LOGIC CIRCUIT EMPLOYING NON-VOLATILE FERROMAGNETIC MEMORY CELLSĪntifuse circuit of inverter type and method of programming the same LOW FREQUENCY DETECTOR INCLUDING COMMON INPUT VOLTAGE SENSOR